UEMI-II - The Quest to Build a Working Computer from just Logic Gates, Transistors and Diodes

UEMI-II is a very simple computer, conceived after a visit to Bletchley Park just before the COVID pandemic. Unlike the historic machines built with thermionic valves, this design relies on legacy 74HC-series logic gates, transistors, diodes, and other discrete components—a modern homage to early 1970s computing principles.

At its core, the computer features:

• 32 × 8-bit CMOS RAM

• 3+8 BIT instruction + operand

• Support for basic arithmetic operations, conditional branching, and other essential functions

Together, these elements qualify UEMI-II as a fully operational computer, albeit on a very small scale.

This project remains very much a work in progress. Construction advances in between a full-time job, other hobbies, and occasional long pauses. Below is a breakdown of the components assembled so far.

The first card manufactured for UEMI-II was the clock and program counter. At its heart is a simple 555 oscillator, which provides the system clock frequency. There’s also provision for injecting an external clock source, allowing experiments to determine how fast the computer can run before reaching its limits.

Instruction execution is organized into four cycles—labelled A, B, C, and D—with a Trigger (T) signal embedded within each cycle. The trigger ensures data transfers occur cleanly, avoiding race conditions, and enables register latches at the right moment. Both the cycles and the trigger are broadcast on the common bus and are visually indicated by five LEDs mounted at the bottom of the card.

The cycle functions are as follows:

• A – Instruction Fetch Load the instruction from the current program counter address, along with any necessary register resets.

• B – Program Counter Advance Increment the program counter. This cycle is also used by the instruction card, guided by the ‘micro-code’ diode matrix.

• C – Instruction Execution Dedicated to the instruction card.

• D – Branch/Optional Operations May be used by the instruction card and can optionally assign the data bus value to the program counter (for branching).

• T – Trigger Pulse A short pulse within each cycle that initiates data transfers and enables register latches

I/O and Programmer Card

The next stage of construction was the I/O and programmer card.

• On the left-hand display, the current program counter and data bus status are shown in real time.

• A switch board provides manual control, allowing selection of data, addresses, and direct programming of the RAM.

RAM Card

The RAM chips sit mid-top on the board while the card as a whole consists of:

• Four chips delivering 32 bytes of memory for both program and data storage.

• Additional chips that handle address decoding and buffering, enabling reliable read and write operations to and from the data bus.

Debugging Features

To aid in development and troubleshooting:

• LED indicators are included to monitor read operations during any selected cycle.

• These visual cues will be invaluable for debugging hardware and verifying correct bus activity.

Instruction Card

The Instruction card is currently under development. Its role is to decode the 3-bit instruction set into 16 signal lines
for each of the three active cycles (B, C, and D).

• These signals define how each instruction interacts with the system during its assigned cycle.

• The outputs are routed into a diode matrix, which will be constructed on the green card shown in the design.

• The matrix itself plugs into the socket at the top of the card, providing a flexible way to implement and modify the micro-code logic.

This modular approach allows instructions to be defined and refined by simply reconfiguring the diode matrix, making it easier to experiment with new operations or adjust existing ones.

To be built

Instruction Card and Diode Matrix

The next milestone will be the completion of the Instruction card together with its diode matrix plug-in.

• The matrix maps up to 16 instructions across the three active states (B, C, and D).

• These outputs feed into both the Instruction card and the ALP (Arithmetic Logic Processor) card, ensuring each instruction is executed in a controlled, stepwise manner.

• Branching logic is implemented by setting the program counter from the lower 5-bit operand portion of the instruction.

• Conditional branching is managed via the flag register, which holds >0, =0, and <0 flags. These are set by a special instruction executed immediately before the branch.

  • Normal branching: accomplished in a single step.

  • Conditional branching: requires two steps (flag-setting followed by the branch).

Register Board and ALU

Following the Instruction card, development will move to the register board and ALU.

• The ALU will support basic addition, two’s complement arithmetic, and logical operations.

• By default, all operations are treated as addition, unless overridden by a flag in the flag register.

• This flag is set by a special instruction executed in the prior step, similar to conditional branching.

• Using this approach, the system can effectively expand the 3-bit instruction set into 16 or more functional instructions, though some operations will require two instructions to complete.

Future Expansion and First Program

Beyond the ALU, a further I/O card may be added to allow UEMI-II to interact with the outside world—for example, as a simple controller for a model railway.

For the first program, the goal is to emulate the historic Manchester Baby’s inaugural run, attempting to calculate the highest factor of a number within just 32 bytes of memory. This will be both a technical challenge and a fitting tribute to early computing history.

All Lit Up

Here’s a picture of the system all lit up in its current state:

Architectural Diagram

An architectural diagram of UEMI-II showing the key elements. Note a 4 bit index register and the flag register used for conditional branches and to select arithmetic operations.